In recent years, a small high-capacity secondary battery is used for various electronic equipments such as a mobile phone, a notebook PC and a smart phone. As such a secondary battery, a Li ion cell is exemplified. The secondary battery such as the Li ion cell has a high performance but sometimes causes generation of heat and degradation through over-charge, over-discharge, and short-circuit and so on. Therefore, in order to use such a secondary battery more safely, the protection circuit is necessary. The protection circuit is arranged in the cell pack, monitors over-charge, over-discharge, and over-current, abnormal heat generation and so on and controls the charging and discharging operations.
For example, the protection circuit includes a charge and discharge FET (Field Effect Transistor), a resistance (hereinafter, to be referred to as a “sense resistance”), a temperature detection device and a control circuit. The charge and discharge FET turns on or off a charge and discharge path. As the charge and discharge FET, generally, two MOSFETs (Metal Oxide Semiconductor FETs) having a common drain are formed as a 1-chip circuit. The sense resistance is arranged on the way of the charge and discharge path and detects a charge and discharge current. The temperature detection device detects the temperature of the MOSFET and the protection circuit. As the temperature detection device, a thermistor is exemplified. The control circuit processes data from these detection devices and controls the MOSFETs.
As the cell pack which has such a protection circuit, a pack cell is disclosed in, for example, JP 2007-66748A. This pack cell communicates with a charging device. The pack cell includes a charge FET device. The charge FET device is turned off when the cell is charged up to a full charging state. The control circuit carries out communication processing with the charging device and a control of the charge FET device. In the control circuit, the charge FET device is turned off in the full charging state and is turned on when ii is determined that there no communication with the charging device.
Specifically, this pack cell A includes a secondary battery 1, a charge FET device 91, a discharge FET device 92, a detection resistance (a sense resistance) 2 and a MPU (Micro Processor Unit). The charge FET device 91 and the discharge FET device 92 are connected in series on a power supply path which connects the positive electrode of the secondary battery 1 and the positive terminal (+) of the pack cell A. That is, the drain of the discharge FET device 92 and the drain of the discharge FET device 91 are connected in common. The source of the discharge FET device 92 is connected with the side of the positive electrode of the secondary battery 1. The source of the charge FET device 91 is connected with the positive terminal (+). It should be noted that the gate of the discharge FET device 92 and the gate of the charge FET device 91 are connected with the MPU. Also, the detection resistance 2 (the sense resistance) is provided on a power supply path which connects the negative electrode of the secondary battery 1 and the negative terminal (−) of the pack cell A. The voltage of the detection resistance (the sense resistance) 2 is measured by the MPU.
The discharging operation of this pack cell A can be considered as follows. A load is connected between the positive terminal (+) and the negative terminal (−) in the pack cell A. The MPU turns on the charge FET device 91 and the discharge FET device 92 together by a gate control signal. Thus, the secondary battery 1 begins a discharging operation, so that a discharge current flows through each power supply path. The MPU reads the voltage across the both ends of the detection resistance (the sense resistance) 2 and calculates a discharge current. When the discharge current is larger than a predetermined value, the MPU determines that an extraordinary current flows and turns off the charge FET device 91 and the discharge FET device 92 together by the gate control signal. Thus, a discharge path is blocked off and the discharge current stops. The same operation is carried out when it is determined that the cell voltage reached a desired voltage.
Also, the charging operation of this pack cell A is considered as follows. The charging device is connected between the positive terminal (+) and the negative terminal (−) of the pack cell A. The MPU turns on the charge FET device 91 and the discharge FET device 92 together by the gate control signal. Thus, the secondary battery 1 begins the charging operation and the charge current flows through each power supply path. The MPU reads a voltage across the both ends of the detection resistance (the sense resistance) 2 and calculates a charge current. When the charge current is larger than a predetermined value, the MPU determines that an extraordinary current flows about and the charge FET device 91 and the discharge FET device 92 are turned off together by the gate control signal. Thus, the charge path is blocked off and the charge current stops. The same operation is carried out when it is determined that the cell voltage reached a desired voltage.
As a related technique, a power unit is disclosed in JP 2012-50258A (the international publication WO 2012/026537A1). This power unit includes one or more cell pack and a protection unit. The two or secondary battery connected in serial or in parallel are contained in the one or more cell packs. The protection unit can be electrically connected with the cell pack. The power which is supplied from an external power unit can be stored in each cell pack and is discharged from each cell pack. The cell pack has a pack abnormal output terminal to send a pack extraordinary signal to the protection unit or another cell pack in case of abnormal generation. The protection unit includes a protection-side input/output terminal to be connected with the pack abnormal output terminal and a protection circuit which can block off the current of the cell pack. When a malfunction occurs in the cell pack, a pack extraordinary signal is outputted from the pack abnormal output terminal of the cell pack to the protection-side input/output terminal of the protection unit. The protection unit blocks off the current by the protection circuit when it detects the pack extraordinary signal.
Also, a semiconductor device is disclosed in Japanese Patent 4,756,557 (corresponding to international publication WO 2006/114883A1). This semiconductor device includes a first terminal, a second terminal, a power MOSFET, a current detection means, a resistance means, a comparing circuit and a first MOSFET. The power MOSFET has a drain connected with the first terminal and a source connected with the second terminal. The current detection means detects a current which flows through the power MOSFET. A resistance means is provided between the gate of the power MOSFET and the first terminal. The comparing circuit compares an output signal of the current detection means and a reference signal. The first MOSFET has a gate supplied with the output signal of the comparing circuit, and a drain-source path is connected between the gate of the power MOSFET and the source. The above first terminal and the second terminal can be handled as an external first terminal and an external second terminal.
Also, an AC switching device is disclosed in JP 2000-299634A (corresponding to U.S. Pat. No. 6,392,859B1). This AC switching device is a switching device to use for an AC semiconductor fuse. The switching device includes a p-channel first main semiconductor device and an n-channel second main semiconductor device. The p-channel first main semiconductor device has the first main electrode which is connected with the side of the non-grounding of an AC power supply, the second main electrode provided to oppose to the first main electrode, and a first control electrode which controls the main current which flows through the first and the second main electrode. A first parasitic diode is included which has a cathode region connected with the first main electrode, and an anode region connected with the second main electrode. The n-channel second main semiconductor device has a third main electrode connected with the second main electrode, a fourth main electrode opposing to the third main electrode and connected with the load, and the second control electrode which controls the main current which flows through the third and the fourth main electrodes. A second parasitic diode is included which has an anode region connected with the third main electrode and a cathode region connected with the fourth main electrode.